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Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Pin Description (continued)
PIN
8
9
NAME
V CC_RG
STA_B_2
FUNCTION
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. V CC_RG powers all
circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to
the pin.
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
State A State B Digital Attenuator 2
Logic = 0
Logic = 1
Logic = 0
Logic = 0
Preprogrammed State 1
Preprogrammed State 2
10
STA_A_2
Logic = 0
Logic = 1
Logic = 1
Logic = 1
Preprogrammed State 3
Preprogrammed State 4
14
11
14
15
16
17
18
19
21
24
26
27
29
30
31
32
34
35
37
42
43
44
45
46
47
—
D_ATT_IN_2
D0_2
D1_2
D2_2
D3_2
D_ATT_OUT_2
D4_2
DA_SP
V CC_AMP_2
AMP_IN_2
PD_2
AMP_OUT_2
REG_OUT
AMPSET
AMP_OUT_1
PD_1
AMP_IN_1
V CC_AMP_1
D4_1
D_ATT_OUT_1
D3_1
D2_1
D1_1
D0_1
EP
5-Bit Digital Attenuator RF Input (50 I ), Path 2. Requires a DC-blocking capacitor.
1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
5-Bit Digital Attenuator Output (50 I ), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable.
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set
DA_SP to 0 to select parallel control.
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
Driver Amplifier Input (50 I ), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor.
Power-Down, Path 2. See Table 2 for operation details.
Driver Amplifier Output (50 I ), Path 2. Connect a pullup inductor from AMP_OUT_2 to V CC_ .
Regulator Output. Bypass with a 1 F F capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins V CC_AMP1 and
V CC_AMP2 . Set to logic 0 for 5V.
Driver Amplifier Output (50 I ), Path 1. Connect a pullup inductor from AMP_OUT_1 to V CC_ .
Power-Down, Path 1. See Table 2 for operation details.
Driver Amplifier Input (50 I ), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
5-Bit Digital Attenuator Output (50 I ), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper
RF performance and enhanced thermal dissipation.
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